Responsibilities:

• Carry out the full physical design flow from RTL to GDS—including synthesis, floorplanning, power grid design, placement and routing, and clock tree synthesis — while participating in design and architecture reviews to monitor project milestones
• Assess and enhance physical design methodologies to manage increasingly complex SoC/IP designs under tight, market-driven timelines
• Engage in advanced System-on-a-Chip (SoC) design projects leveraging state-of-the-art process technology nodes for diverse client applications
• Collaborate actively within local teams as well as with remote and multi-site teams
• Actively contributes to full-chip physical verification activities, including DRC and LVS checks as well as EM/IR convergence
• Actively supports the development of full-chip timing constraints, performs full-chip Static Timing Analysis, and contributes to timing signoff for complex, multi-clock, multi-voltage SoCs

Qualifications:

• Electronics/Computer Engineering, Electrical engineering or related degree
• Skilled in Perl, TCL, and Python for automating and optimizing CAD flows
• Solid understanding of digital logic, VHDL/RTL design, and Verilog
• Proven track record of successful completions and tapeouts on advanced FinFET technology nodes (16nm, 12nm, 7nm, 5nm, 3nm), incorporating low-power design methodologies
• Hands-on experience with Synopsys EDA tools such as Fusion Compiler, PrimeTime, IC Validator, and VC Low-Power
• Experience with automated design flows and synthesis processes
• Experience with advanced sign-off processes, including Lint, CDC, LEC, scan, and ECO flows
• Experience in top-level physical design implementation
• Practical experience with place-and-route (PnR), including floorplanning, clock tree synthesis (CTS), physical verification, timing closure, and IR drop analysis
• Practical experience with full-chip and sub-chip Static Timing Analysis, including timing constraint creation and timing closure
• Proficient in power analysis and implementing power optimization techniques
• Hands-on experience with Cadence EDA tools such as Innovus, Tempus, Virtuoso, and Conformal Low-Power